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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
December 2010
FAN4800AS/CS/01S/2S PFC/PWM Controller Combination
Features
Pin-to-Pin Compatible with ML4800 and FAN4800 and CM6800 and CM6800A PWM Configurable for Current Mode or Feedforward Voltage-Mode Operation Internally Synchronized Leading-Edge PFC and Trailing-Edge PWM in One IC Low Operating Current Innovative Switching-Charge Multiplier Divider Average-Current Mode for Input-Current Shaping PFC Over-Voltage and Under-Voltage Protections PFC Feedback Open-Loop Protection Cycle-by-Cycle Current Limiting for PFC/PWM Power-on Sequence Control and Soft-Start Brownout Protection Interleaved PFC/PWM Switching Improved Efficiency at Light Load fRTCT=4*fPFC=4*fPWM for FAN4800AS/01S fRTCT=4*fPFC=2*fPWM for FAN4800CS/02S
Description
The highly integrated FAN4800AS/CS/01S/02S parts are specially designed for power supplies that consist of boost PFC and PWM. They require very few external components to achieve versatile protections / compensation. They are available in 16-pin DIP and SOP packages. The PWM can be used in either current or voltage mode. In voltage mode, feed-forward from the PFC output bus can reduce the secondary output ripple. Compared with older productions, ML4800 and FAN4800, FAN4800AS/CS/01S/02S have lower operation current that saves power consumption in external devices. FAN4800AS/CS/01S/02S have accurate 49.9% maximum duty of PWM that makes the hold-up time longer. Brownout protection and PFC softstart functions available in this series are not available in ML4800 and FAN4800. To evaluate FAN4800AS/CS/01S/02S for replacing existing FAN4800 and ML4800 boards, five things must be completed before the fine-tuning procedure: 1. 2. Change RAC resister from the old value to a higher resister: between 6M to 8M. Change RT/CT pin from the existing values to RT=6.8k and CT=1000pF to have fPFC=64kHz and fPWM=64kHz. The VRMS pin needs to be 1.224V at VIN=85 VAC for universal input application from line input from 85VAC to 270VAC. At full load, the average VVEA needs to be ~4.5V and the ripple of VVEA needs to be less than 400mV. For the Soft-Start pin, the soft-start current has been reduced to half the FAN4800 capacitor.
Applications
Desktop PC Power Supply Internet Server Power Supply LCD TV, Monitor Power Supply UPS Battery Charger DC Motor Power Supply Monitor Power Supply Telecom System Power Supply Distributed Power 5. 4. 3.
There are two differences from FAN4800A/C/01/02 to FAN4800AS/CS/01S/02S: 1. 2. Under-voltage protection extended to one second. debounce time is
Related Resources
AN-8027 - FAN480X PFC+PWM Combination Controller Application
PWM gate clamp voltage is raised to 19V.
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Ordering Information
Part Number
FAN4800ASNY FAN4800ASMY FAN4800CSNY FAN4800CSMY FAN4801SNY FAN4801SMY FAN4802SNY FAN4802SMY
Operating Temperature Range
-40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package
16-Pin Dual Inline Package (DIP) 16-Pin Small Outline Package (SOP) 16-Pin Dual Inline Package (DIP) 16-Pin Small Outline Package (SOP) 16-Pin Dual Inline Package (DIP) 16-Pin Small Outline Package (SOP) 16-Pin Dual Inline Package (DIP) 16-Pin Small Outline Package (SOP)
Packing Method
Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel Tube Tape & Reel
Application Diagram
Figure 1.
Typical Application, Current Mode
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Application Diagram
IEA IAC ISENSE VRMS SS FBPWM RT/CT VREF RAMP
VEA FBPFC VREF VDD OPFC OPWM GND ILIMIT VDD
VREF
Figure 2.
Typical Application, Voltage Mode
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Block Diagram
Figure 3.
FAN4800AS/CS Function Block Diagram
Figure 4.
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
FAN4801S/02S Function Block Diagram
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Marking Information
F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code YY - 2-Digit Week Code TT - 2-Digit Die-Run Code T - Package Type (N:DIP) P - Y: Green Package M - Manufacture Flow Code
Figure 5.
DIP Top Mark
F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die-Run Code T - Package Type (M:SOP) P - Y: Green Package M - Manufacture Flow Code
Figure 6.
SOP Top Mark
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Pin Configuration
Figure 7.
Pin Configuration (Top View)
Pin Definitions
Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
IEA IAC ISENSE VRMS SS FBPWM RT/CT RAMP ILIMIT GND OPWM OPFC VDD VREF FBPFC VEA
Description
Output of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulse width for PFC gate drive. Input AC Current. For normal operation, this input provides current reference for the multiplier. The suggested maximum IAC is 100A. PFC Current Sense. The non-inverting input of the PFC current amplifier and the output of multiplier and PFC ILIMIT comparator. Line-Voltage Detection. The pin is used for the PFC multiplier. PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 10A constant current source. The voltage on FBPWM is clamped by SS during startup. If a protection condition occurs and/or PWM is disabled, the SS pin is quickly discharged. PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. Oscillator RC Timing Connection. Oscillator timing node; timing set by RT and CT. PWM RAMP Input. In current mode, this pin functions as the current-sense input; when in voltage mode, it is the feedforward sense input from PFC output 380V (feedforward ramp). Peak Current Limit Setting for PWM. The peak current limits setting for PWM. Ground. PWM Gate Drive. The totem-pole output drive for PWM MOSFET. This pin is internally clamped under 19V to protect the MOSFET. PFC Gate Drive. The totem-pole output drive for PFC MOSFET. This pin is internally clamped under 15V to protect the MOSFET. Supply. The power supply pin. The threshold voltages for startup and turn-off are 11V and 9.3V, respectively. The operating current is lower than 10mA. Reference Voltage. Buffered output for the internal 7.5V reference. Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. Output of PFC Voltage Amplifier. The error amplifier output for PFC voltage feedback loop. A compensation network is connected between this pin and ground.
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(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD VH VL VIEA VN IAC IREF IPFC-OUT IPWM-OUT PD JA JC TJ TSTG TL ESD DC Supply Voltage
Parameter
SS, FBPWM, RAMP, OPWM, OPFC, VREF IAC, VRMS, RT/CT, ILIMIT, FBPFC, VEA IEA ISENSE Input AC Current VREF Output Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink Power Dissipation TA < 50C Thermal Resistance (Junction to Air) Thermal Resistance (Junction to Case) Operating Junction Temperature Storage Temperature Range Lead Temperature(Soldering) Electrostatic Discharge Capability Human Body Model Charged Device Model DIP SOP DIP SOP
Min.
-0.3 -0.3 0 -5.0
Max.
30 30.0 7.0 VVREF+0.3 0.7 1 5 0.5 0.5 800 80.80 104.10 35.38 40.41
Unit
V V V V V mA mA A A mW C/W C/W C C C kV
-40 -55
+125 +150 +260 5.0 1.5
Notes: 1. All voltage values, except differential voltage, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Min.
-40
Typ.
Max.
+105
Unit
C
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Electrical Characteristics
Unless otherwise noted, VDD=15V, TA= 25C, TA=TJ, RT=6.8k, and CT=1000pF.
Symbol
VDD Section VDD-OP IDD ST IDD-OP VTH-ON VTH VDD-OVP VDD-OVP Oscillator fOSC-RT/CT fOSC fDV fDT fTV fRV IOSC-DIS fRANGE tPFC-DEAD VREF VVREF VVREF1 VVREF2 VVREF-DT VVREF-TV VVREF-LS IREF-MAX VPFC-OVP VPFC-OVP VVEAOFF
Parameter
Continuously Operating Voltage Startup Current Operating Current Turn-on Threshold Voltage Hysteresis VDD OVP VDD OVP Hysteresis RT/CT Frequency PFC & PWM Frequency PWM Frequency Voltage Stability
(3) (3) (3)
Conditions
Min.
Typ.
Max.
26
Unit
V A mA V V V V
VDD=VTH-ON-0.1V; OPFC OPWM Open VDD=13V; OPFC OPWM Open 2.0 10 1.3 27
30 2.6 11 28 1
80 5.0 12 1.9 29
RT=6.8k, CT=1000pF RT=6.8k, CT=1000pF 11V VDD 22V -40C ~ +105C Line, Temperature Valley to Peak VRAMP=0V, VRT/CT=2.5V RT = 6.8k, CT = 1000pF IREF=0mA, CREF=0.1F CREF=0.1F, IREF=0mA to 3.5mA VVDD=14V, Rise/Fall Time > 20s CREF=0.1F, VVDD=11V to 22V -40C ~ +105C Line, Load, Temp
(3)
240 60 120
256 64 128
268 67 134 2 2
kHz kHz % % kHz V mA kHz ns V mV mV % V mV mA
Temperature Stability Ramp Voltage Discharge Current Frequency Range PFC Dead Time Reference Voltage
Total Variation (PFC & PWM)
58 2.8 6.5 50 400 7.4 600 7.5 30
70 15.0 75 800 7.6 50 25 0.4 0.5 7.65 25
Load Regulation of Reference Voltage Line Regulation of Reference Voltage Temperature Stability Total Variation
(3) (3)
7.35 5 5 2.70 200 0.2 2.75 250 0.3
Long-Term Stability Maximum Current
TJ=125C, 0 ~ 1000HRs VVREF > 7.35V
PFC OVP Comparator Over-Voltage Protection PFC OVP Hysteresis VEA Voltage OFF OPFC Voltage Level on FBPFC to Enable OPWM During Startup Hysteresis 2.80 300 0.4 V mV V
Low-Power Detect Comparator VIN OK Comparator VRD-FBPFC VRD-FBPFC 2.3 1.15 2.4 1.25 2.5 1.35 V V
Continued on the following page...
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=15V, TA= 25C, TA=TJ, RT=6.8k, and CT=1000pF.
Symbol
Voltage Error Amplifier VREF AV Gmv IFBPFC-L IFBPFC-H IBS VVEA-H VVEA-L GmI VOFFSET VIEA-H VIEA-L IL IH AI
(3)
Parameter
Reference Voltage Open-Loop Gain
(3)
Conditions
Min.
2.45 35
Typ.
2.50 42 70 50 -50
Max.
2.55 90 -40 1
Unit
V dB umho A A A V V umho mV V V A A dB
Transconductance Maximum Source Current Maximum Sink Current Input Bias Current Output High Voltage on VVEA Output Low Voltage on VVEA Transconductance Input Offset Voltage Output High Voltage Output Low Voltage Source Current Sink Current Open-Loop Gain
VNONINV=VINV, VVEA=3.75V VFBPFC=2V, VVEA=1.5V VFBPFC=3V, VVEA=6V
50 40 -1 5.8
6.0 0.1 0.4 100 10 7.4 0.1 50 -50 -35 50 8.0 0.4
Current Error Amplifier VNONINV=VINV, VIEA=3.75V VVEA=0V, IAC Open 78 -10 6.8 VISENSE=-0.6V, VIEA=1.5V VISENSE=+0.6V, VIEA=4.0V 40 VFBPFC=VPFC-UVP to FBPFC OPEN, 470pF from FBPFC to GND 0.4 35 88
TriFault DetectTM tFBPFC_OPEN VPFC-UVP Time to FBPFC Open PFC Feedback Under-Voltage Protection Input for AC Current
(3)
2 0.5
4 0.6
ms V
Gain Modulator IAC Multiplier Linear Range IAC=17.67A, VRMS=1.080V VFBPFC=2.25V IAC=20.00A, VRMS=1.224V VFBPFC=2.25V GAIN GAIN Modulator
(4)
0 7.500 6.367 3.801 0.950 0.660
100 9.000 10.500 7.004 4.182 1.045 0.726 2 7.704 4.600 1.149 0.798
A
IAC=25.69A, VRMS=1.585V VFBPFC=2.25V IAC=51.62A, VRMS=3.169V VFBPFC=2.25V IAC=62.23A, VRMS=3.803V VFBPFC=2.25V
BW VO(gm)
Bandwidth
(3)
IAC=40A IAC=20A, VRMS=1.224V VFBPFC=2.25V 0.710
kHz 0.885 V
Output Voltage=5.7k x (ISENSEIOFFSET) Peak Current Limit Threshold Voltage, Cycle-by-Cycle Limit PFC ILIMIT-Gain Modulator Output
0.798
PFC ILIMIT Comparator VPFC-ILIMIT VPK -1.35 IAC=17.67A, VRMS=1.08V VFBPFC=2.25V 200 -1.20 -1.05 V mV
Continued on the following page...
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=15V, TA= 25C, TA=TJ, RT=6.8k, and CT=1000pF.
Symbol
PFC Output Driver VGATE-CLAMP VGATE-L VGATE-H tR tF DPFC-MAX DPFC-MIN Brownout VRMS-UVL VRMS-UVH VRMS-UVP tUVP Soft Start VSS-MAX ISS VPWM-ILIMIT tPD tPWM-BNK VVRMS-L VVRMS-H VVEA-L VVEA-H ITC VGATE-CLAMP VGATE-L VGATE-H tR tF DPWM-MAX VPWM-LS
Parameter
Gate Output Clamping Voltage Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time Maximum Duty Cycle Minimum Duty Cycle VRMS Threshold Low VRMS Threshold High Hysteresis Under Voltage Protection Debounce Time Maximum Voltage Soft-Start Current Threshold Voltage Propagation Delay to Output Leading-Edge Blanking Time RMS AC Voltage Low RMS AC Voltage High VEA LOW VEA HIGH Source Current from FBPFC Gate Output Clamping Voltage Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time Maximum Duty Cycle PWM Comparator Level Shift VDD=22V VDD=15V VDD=22V
Conditions
Min.
13 8 40 40 94
Typ.
15
Max.
17 1.5
Unit
V V V
VDD=15V, IO = 100mA VDD=13V, IO = 100mA VDD=15V, CL=4.7nF, O/P= 2V to 9V VDD=15V; CL=4.7nF, O/P= 9V to 2V VIEA<1.2V VIEA>4.5V When VRMS=1.05V at 75VRMS When VRMS=1.9V at 85*1.414 1.03 1.88 750 850 1.05 1.90 850 1000
70 60 97
120 110
ns ns %
0 1.08 1.94 950 1150
% V V mV ms
9.5
10.0 10
10.5
V A
PWM ILIMIT Comparator 0.95 170 When VVRMS =1.95V at 132VRMS When VVRMS =2.45V at 150VRMS When VVEA= 1.95V at 30% Loading When VVEA= 2.45V at 40% Loading 1.90 2.40 1.90 2.40 18 18 8 30 30 49.0 1.3 60 50 49.5 1.5 120 110 50.0 1.8 1.00 250 250 1.95 2.45 1.95 2.45 20 19 350 2.00 2.50 2.00 2.50 22 20 1.5 1.05 V ns ns V V V V A V V V ns ns % V
Range (FAN4801S/02S)
PWM Output Driver VDD=15V, IO=100mA VDD=13V, IO=100mA VDD=15V, CL=4.7nF VDD=15V, CL=4.7nF
Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. This GAIN is the maximum gain of modulation with a given VRMS voltage when VVEA is saturated to HIGH.
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Typical Characteristics
20.0 18.0 16.0 14.0 28.04 28.02 28.00
VDD-OVP(V)
IDD-ST(uA)
27.98 27.96 27.94 27.92 27.90 27.88 27.86
12.0 10.0 8.0 6.0 4.0 2.0 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
Figure 8.
65.0 64.9 64.8
IDD-ST vs. Temperature
7.520 7.515 7.510
Figure 9.
VDD-OVP vs. Temperature
FOSC(kHz)
VVREF(V)
64.7 64.6 64.5 64.4 64.3 64.2 -40 -25 -10 5 20 35 50 65 80 95 110 125
7.505 7.500 7.495 7.490 7.485 7.480 7.475 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 10.
2.742 2.740
fOSC vs. Temperature
2.502 2.500 2.498
Figure 11.
VVREF vs. Temperature
VPFC-OVP(V)
VREF(V)
2.738 2.736 2.734 2.732 2.730 -40 -25 -10 5 20 35 50 65 80 95 110 125
2.496 2.494 2.492 2.490 2.488 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 12.
74 73
VPFC-OVP vs. Temperature
94 92 90
Figure 13.
VREF vs. Temperature
GmV(umho)
GmI(umho)
-25 -10 5 20 35 50 65 80 95 110 125
73 72 72 71 -40
88 86 84 82 80 78 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 14.
-1.177 -1.178
GmV vs. Temperature
1.010 1.009
Figure 15.
GmI vs. Temperature
VPFC-ILIMIT (V)
-1.179 -1.180 -1.181 -1.182 -1.183 -40 -25 -10 5 20 35 50 65 80 95 110 125
VPWM-ILIMIT (V)
1.008 1.007 1.006 1.005 1.004 1.003 1.002 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 16.
VPFC-ILIMIT vs. Temperature
11
Figure 17.
VPWM-ILIMIT vs. Temperature
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(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Typical Characteristics
1.048 1.047 1.046 867.5 867.0 866.5
VRMS-UVP(mV)
VRMS-UVP(V)
1.045 1.044 1.043 1.042 1.041 1.040 1.039 1.038 -40 -25 -10 5 20 35 50 65 80 95 110 125
866.0 865.5 865.0 864.5 864.0 863.5 863.0 862.5 862.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 18.
14.7 14.6
VRMS-UVP vs. Temperature
19.00 18.95 18.90 18.85 18.80 18.75 18.70 18.65 18.60 18.55 18.50 5 20 35 50 65 80 95 110 125
Figure 19.
VRMS-UVP vs. Temperature
VGATE-CLAMP-PFC (V)
14.5 14.4 14.3 14.2 14.1 14.0 13.9 -40 -25 -10
VGATE-CLAMP-PWM(V)
-40 -25 -10
5
20
35
50
65
80
95 110 125
Figure 20.
96.06 96.04 96.02
VGATE-CLAMP-PFC vs. Temperature
Figure 21.
49.80 49.75
VGATE-CLAMP-PWM vs. Temperature
DPFC-MAX(%)
96.00 95.98 95.96 95.94 95.92 95.90 95.88 -40 -25 -10 5 20 35 50 65 80 95 110 125
DPWM-MAX (%)
49.70 49.65 49.60 49.55 49.50 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 22.
10.1 10.0 9.9 9.8
DPFC-MAX vs. Temperature
21.0 20.8 20.6
Figure 23.
DPWM-MAX vs. Temperature
ISS(uA)
9.6 9.5 9.4 9.3 9.2 9.1 -40 -25 -10 5 20 35 50 65 80 95 110 125
ITC(uA)
9.7
20.4 20.2 20.0 19.8 19.6 19.4 -40 -25 -10 5 20 35 50 65 80 95 110 125
Figure 24.
ISS vs. Temperature
Figure 25.
ITC vs. Temperature
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Functional Description
The FAN4800AS/CS/01S/02S consist of an average current controlled, continuous-boost, Power Factor Correction (PFC) front-end and a synchronized Pulse Width Modulator (PWM) back-end. The PWM can be used in current or voltage mode. In voltage mode, feedforward from the PFC output bus can help improve the line regulation of PWM. In either mode, the PWM stage uses conventional trailing-edge, duty-cycle modulation. This proprietary leading / trailing edge modulation results in a higher usable PFC error amplifier bandwidth and can significantly reduce the size of the PFC DC bus capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). In addition to power factor correction, a number of protection features are built into this series. They include soft-start, PFC over-voltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout (UVLO).
xK (1) VRMS 2 Note that the output current of the gain modulator is limited around 159A and the maximum output voltage of the gain modulator is limited to 159A x 5.7k=0.906V. This 0.906V also determines the maximum input power. However, IGAINMOD cannot be measured directly from ISENSE. ISENSE=IGAINMOD - IOFFSET and IOFFSET can only be measured when VVEA is less than 0.5V and IGAINMOD is 0A. Typical IOFFSET is around 31A ~ 48A.
IGAINMOD =
I AC x (VEA - 0.7 )
Selecting RAC for the IAC Pin
The IAC pin is the input of the gain modulator and also a current mirror input that requires current input. Selecting a proper resistor, RAC, provides a good sine wave current derived from the line voltage and helps program the maximum input power and minimum input line voltage. RAC=VIN peak x 56k. For example, if the minimum line voltage is 75VAC, the RAC=75 x 1.414 x 56k=6M.
Gain Modulator
The gain modulator is the heart of the PFC, as the circuit block controls the response of the current loop to line voltage waveform and frequency, RMS line voltage, and PFC output voltages. There are three inputs to the gain modulator: 1. A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is fed into the gain modulator at IAC. Sampling current in this way minimizes ground noise, required in high-power, switching-power conversion environments. The gain modulator responds linearly to this current. 2. A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at VRMS. The output of the gain modulator is inversely proportional to VRMS (except at unusually low values of VRMS, where special gain contouring takes over to limit power dissipation of the circuit components under brownout conditions). 3. The output of the voltage error amplifier, VEA. The gain modulator responds linearly to variations in VVEA. The output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. This current is applied to the virtual ground (negative) input of the current error amplifier. In this way, the gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current draw of the PFC from the power line. The general form of the output of the gain modulator is:
Current Amplifier Error, IEA
The current error amplifier's output controls the PFC duty cycle to keep the average current through the boost inductor a linear function of the line voltage. At the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current, which results in a negative voltage being impressed upon the ISENSE pin. The negative voltage on ISENSE represents the sum of all currents flowing in the PFC circuit and is typically derived from a current-sense resistor in series with the negative terminal of the input bridge rectifier. The inverting input of the current error amplifier is a virtual ground. Given this fact, and the arrangement of the duty cycle modulator polarities internal to the PFC, an increase in positive current from the gain modulator causes the output stage to increase its duty cycle until the voltage on ISENSE is adequately negative to cancel this increased current. Similarly, if the gain modulator's output decreases, the output duty cycle decreases to achieve a less negative voltage on the ISENSE pin.
PFC Cycle-By-Cycle Current Limiter
In addition to being a part of the current feedback loop, the ISENSE pin is a direct input to the cycle-by-cycle current limiter for the PFC section. If the input voltage at this pin is less than -1.15V, the output of the PFC is disabled until the protection flip-flop is reset by the clock pulse at the start of the next PFC power cycle.
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
TriFault DetectTM
To improve power supply reliability, reduce system component count, and simplify compliance to UL1950 safety standards; the FAN4800AS/CS/01S/02S includes TriFault DetectTM technology. This feature monitors FBPFC for certain PFC fault conditions. In a feedback path failure, the output of the PFC could exceed safe operating limits. With such a failure, FBPFC exceeds its normal operating area. Should FBPFC go too low, too high, or open; TriFault DetectTM senses the error and terminates the PFC output drive. TriFault Detect is an entirely internal circuit. It requires no external components to serve its protective function.
Error Amplifier Compensation
The PWM loading of the PFC can be modeled as a negative resistor because an increase in the input voltage to the PWM causes a decrease in the input current. This response dictates the proper compensation of the two transconductance error amplifiers. Figure 26 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. The current-loop compensation is returned to VREF to produce a soft-start characteristic on the PFC. As the reference voltage increases from 0V, it creates a differentiated voltage on IEA, which prevents the PFC from immediately demanding a full duty cycle on its boost converter. Complete design is discussed in application note AN-6078SC. There is an RC filter between Rsense and ISENSE pin. There are two reasons to add a filter at the ISENSE pin: 1. Protection: During startup or inrush current conditions, there is a large voltage across Rsense, the sensing resistor of the PFC boost converter. It requires the ISENSE filter to attenuate the energy. 2. To reduce inductance, L, the boost inductor. The ISENSE filter also can reduce the boost inductor value since the ISENSE filter behaves like an integrator before the ISENSE pin, which is the input of the current error amplifier, IEA. The ISENSE filter is an RC filter. The resistor value of the ISENSE filter is between 100 and 50 because IOFFSET x RFILTER can generate a negative offset voltage of IEA. Selecting an RFILTER equal to 50 keeps the offset of the IEA less than 3mV. Design the pole of the ISENSE filter at fPFC/6, one sixth of the PFC switching frequency, so the boost inductor can be reduced six times without disturbing the stability. The capacitor of the ISENSE filter, CFILTER, is approximately 100nF.
PFC Over-Voltage Protection
In the FAN4800AS/CS/01S/02S, the PFC OVP comparator serves to protect the power circuit from being subjected to excessive voltages if the load changes suddenly. A resistor divider from the high-voltage DC output of the PFC is fed to FBPFC. When the voltage on FBPFC exceeds 2.75V, the PFC output driver is shut down. The PWM section continues to operate. The OVP comparator has 250mV of hysteresis and the PFC does not restart until the voltage at FBPFC drops below 2.5V. VDD OVP can also serve as a redundant PFC OVP protection. VDD OVP threshold is 28V with 1V hysteresis.
Selecting PFC Rsense
Rsense is the sensing resistor of the PFC boost converter. During the steady state, line input current x Rsense equals IGAINMOD x 5.7k. At full load, the average VVEA needs to around 4.5V and ripple on the VEA pin needs to be less than 400mV. Choose the resistance of the sensing resistor:
RSENSE =
( 4.5 - 0.7 ) x 5.7K x IAC x Gain x VIN x 2 x ( 5.6 - 0.7 ) x Line _ Input _ Power
2
(2)
where 5.6 is VVEA maximum output voltage.
PFC Soft-Start
PFC startup is controlled by VVEA level. Before the FBPFC voltage reaches 2.4V, the VVEA level is around 2.8V. At 90VAC, the PFC soft-start time is 90ms.
PFC Brownout
The AC UVP comparator monitors the AC input voltage. The PFC is disabled as AC input lowers, causing VRMS to be less than 1.05V. Figure 26. Compensation Network Connection for the Voltage and Current Error Amplifiers
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Two-Level PFC Function
To improve the efficiency, the system can reduce PFC switching loss at low line and light load by reducing the PFC output voltage. The two-level PFC output of the FAN4801S/02S can be programmable. As Figure 27 shows, FAN4801S/02S detect the voltage of VEA and VRMS pins to determine if the system operates low line and light load. At the second-level PFC, there is a current of 20A through RF2 from the FBPFC pin. The second-level PFC output voltage can be calculated as.
Output RF1 + RF 2 x ( 2.5V - 20 A x RF 2 ) RF 2
Pulse Width Modulator (PWM)
The operation of the PWM section is straightforward, but there are several points that should be noted. Foremost among these is the inherent synchronization of PWM with the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage-mode operation. In currentmode applications, the PWM ramp (RAMP) is usually derived directly from a current-sensing resistor or current transformer in the primary side of the output stage. It is thereby representative of the current flowing in the converter's output stage. ILIMIT, which provides cycle-by-cycle current limiting, is typically connected to RAMP in such applications. For voltage-mode operation and certain specialized applications, RAMP can be connected to a separate RC timing network to generate a voltage ramp against which FBPWM is compared. Under these conditions, the use of voltage feedforward from the PFC bus can assist in line regulation accuracy and response. As in current-mode operation, the ILIMIT input is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage, as this function is generally performed on the output side of the PWM's isolation boundary. To facilitate the design of opto-coupler feedback circuitry, an offset has been built into the PWM's RAMP input that allows FBPWM to command a 0% duty cycle for input voltages below typical 1.5V.
(3)
For example, if the second-level PFC output voltage is expected as 300V and normal voltage is 387V, according to the equation, RF2 is 28k RF1 is 4.3M. The programmable range of second level PFC output voltage is 340V ~ 300V.
PWM Cycle-by-Cycle Current Limiter
The ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin exceed 1V, the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. When the ILIMIT triggers the cycle-by-cycle bi-cycle current, it limits the PWM duty cycle mode and the power dissipation is reduced during the dead-short condition.
Figure 27.
Two-Level PFC Scheme
Oscillator (RT/CT)
The oscillator frequency is determined by the values of RT and CT, which determine the ramp and off-time of the oscillator output clock: 1 fRT / CT = (4) tRT / CT + tDEAD The dead time of the oscillator is derived from the following equation:
VREF - 1 tRT / CT = CT x RT x ln VREF - 3.8 at VREF=7.5V and tRT/CT=CT x RT x 0.56.
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if the voltage on FBPFC is less than its nominal 2.4V. Once the voltage reaches 2.4V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, soft-start begins.
(5)
PWM Soft-Start (SS)
PWM startup is controlled by selection of the external capacitor at soft-start. A current source of 10A supplies the charging current for the capacitor and startup of the PWM begins at 1.5V.
The dead time of the oscillator is determined using:
2.8V x CT = 360 x CT (6) 7.78mA The dead time is so small (tRT/CT>>tDEAD) that the operating frequency can typically be approximated by: tDEAD =
fRT / CT =
1 tRT / CT
(7)
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
PWM Control (RAMP)
When the PWM section is used in current mode, RAMP is generally used as the sampling point for a voltage, representing the current in the primary of the PWM's output transformer. The voltage is derived either from a current-sensing resistor or a current transformer. In voltage mode, RAMP is the input for a ramp voltage generated by a second set of timing components (RRAMP, CRAMP) that have a minimum value of 0V and a peak value of approximately 6V. In voltage mode, feedforward from the PFC output bus is an excellent way to derive the timing ramp for the PWM stage.
Leading/Trailing Edge Modulation
Conventional PWM techniques employ trailing-edge modulation, in which the switch turns on right after the trailing edge of the system clock. The error amplifier output is then compared with the modulating ramp up. The effective duty cycle of the trailing-edge modulation is determined during the on-time of the switch. In the case of leading-edge modulation, the switch is turned off exactly at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch is turned on. The effective duty-cycle of the leading-edge modulation is determined during off-time of the switch.
Generating VDD
After turning on the FAN4800AS/CS/01S/02S at 11V, the operating voltage can vary from 9.3V to 28V. The threshold voltage of the VDD OVP comparator is 28V and its hysteresis is 1V. When VDD reaches 28V, OPFC is LOW and the PWM section is not disturbed. There are two ways to generate VDD: use auxiliary power supply around 15V or use bootstrap winding to self-bias the FAN4800AS/CS/01S/02S system. The bootstrap winding can be taped from the PFC boost choke or the transformer of the DC-to-DC stage.
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Physical Dimensions
19.68 18.66
A
16
9
6.60 6.09
1
8
(0.40)
TOP VIEW
0.38 MIN 5.33 MAX 3.42 3.17 3.81 2.92 2.54 0.58 A 0.35 1.78 1.14 17.78
SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1
Figure 28.
8.13 7.62
0.35 0.20 8.69
15 0
16-Pin, Dual In-Line Package (DIP), JEDEC MS-001, .300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
Physical Dimensions
Figure 29.
16-Pin Small Outline Package (SOIC), JEDEC MS-012, .150", Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1 www.fairchildsemi.com 18
FAN4800AS/CS/01S/02S -- PFC/PWM Controller Combination
(c) 2010 Fairchild Semiconductor Corporation FAN4800AS/CS/01S/02S * Rev. 1.0.1
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